1. Field of the Invention
The present invention relates to a semiconductor memory device having memory cells divided into a plurality of separate blocks.
2. Description of the Prior Art
In recent years, dynamic metal-oxide semiconductor (MOS) random access memory (RAM) devices have been enlarged to 64 kbits (precisely, 65,536 bits). Thus, as the integration density has become higher, the number of memory cells connected to one sense amplifier for the read operation has become higher and, accordingly, the load on each sense amplifier has also become higher, thus reducing the speed of the read operation. In order to reduce the load on each sense amplifier, a prior art 64 kbits MOS RAM device uses two series of sense amplifiers. That is, the memory cells, sense amplifiers, row address decoders, and the like are divided into two blocks, each with 32 kbits.
Further, as the integration density has become higher, the pitch in the column direction, i.e., the distance between bit lines, has also become smaller, while, column address decoders have become larger due to the increase in the number of address bits. As a result, it has become difficult to arrange one column address decoder for each bit line pair. Therefore, an arrangement has been proposed where one column address decoder is used for every two bit line pairs, four bit line pairs, or the like. In this case, two sense line pairs, four sense line pairs, or the like are provided for each block. Of course, decoders for selecting such sense line pairs are necessary, however, such decoders are separated from the block-divided elements and, accordingly, the presence of such decoders negligibly reduces the integration density.
In a prior art block-divided device in which one column decoder is provided for two or more bit line pairs, i.e., two or more sense line pairs are provided for each block, the arrangement of sense lines is the same in all the blocks. As a result, when a write operation is performed upon a first pair of sense lines, and simultaneously, a read operation is performed upon a second pair of sense lines adjacent to the first pair of sense lines, noise generated by the first pair of sense lines is superposed on each line of the second pair of sense lines due to the capacitance between the adjacent lines, impurity diffusion regions, and the like. As a result, the read operation from the second pair of sense lines may be incorrectly carried out. Note that a read operation carried out simultaneously with a write operation, i.e., a read operation during the write access mode, is a so-called refresh operation. Such a refresh operation is also carried out during the read access mode, and in addition, is independently carried out during a no access mode, i.e., during the refresh mode. Regardless of what mode this prior art device is in, a read operation carried out simultaneously with a write operation can result in excessive noise being applied to the sense lines and an error in the read operation.